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automotive power data sheet rev. 1.0, 2013-06-05 spoc - BTS5482SF spi power controller for advanced front light control
data sheet 2 rev. 1.0, 2013-06-05 spoc - BTS5482SF 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 pin assignment spoc - BTS5482SF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.2 thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1 power supply modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 power stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1 output on-state resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.2 input circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.3 power stage output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.4 inverse current behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.5 external driver control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.6 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7 protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.1 inrush state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.2 operative state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.3 fault state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.4 timers and n retry counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.5 undervoltage restarts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.6 reverse polarity protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.7 over voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.8 loss of ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.9 loss of v s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.10 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8 diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8.1 diagnosis word at spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.2 load current sense diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.3 switch bypass diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.4 open load in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.1 spi signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.2 daisy chain capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.3 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.5 spi protocol 8 bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9.6 register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 10 application description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table of contents
spoc - BTS5482SF data sheet 3 rev. 1.0, 2013-06-05 11 package outlines spoc - BTS5482SF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 12 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
pg-dso-36-43 type package marking spoc - BTS5482SF pg-dso-36-43 BTS5482SF data sheet 4 rev. 1.0, 2013-06-05 for advanced front light control spi power controller spoc - BTS5482SF 1overview features ? 8 bit serial peripheral interface for control and diagnosis ? integrated control for two external smart power switches ? 3.3 v and 5 v compatible logic pins ? very low stand-by current ? enhanced electromagnet ic compatibility (emc) for bulbs as well as leds with increased slew rate ? stable behavior at under voltage ? device ground independent from load ground ? green product (rohs-compliant) ? aec qualified description the spoc - BTS5482SF is a four channel high-side smart power switch in pg-dso-36-43 package providing embedded protective functions. it is especially designe d to control standard exterior lighting in automotive applications. in order to use the same hardware, the device can be configured to bulb or led mode for channel 2 and channel 3. as a result, both load types are opti mized in terms of switching and diagnosis behavior. it is specially designed to drive exterior lamps up to 65w, 27w, 10w and hidl. product summary operating voltage power switch v s 4.5 ? 28 v logic supply voltage v dd 3.0?5.5v supply voltage for load dump protection v s(ld) 40 v maximum stand-by current at 25 c i s(stb) 4.5 a typical on-state resistance at t j = 25 c channel 0, 1 channel 2, 3 r ds(on,typ) 4m ? 15 m ? maximum on-state resistance at t j = 150 c channel 0, 1 channel 2, 3 r ds(on,max) 8.5 m ? 28 m ? spi access frequency f sclk(max) 5mhz
spoc - BTS5482SF overview data sheet 5 rev. 1.0, 2013-06-05 configuration and status diagnosis ar e done via spi. the spi is daisy chai n capable. the device provides a current sense signal per channel that is multiplexed to th e diagnosis pin is. it can be enabled and disabled via spi commands. an over load and over temperature flag is provided in the spi diagnosi s word. a multiplexed switch bypass monitor provides short-circuit to v s diagnosis. in off-state a current source can be switched to the output of one selected channel in order to detect an open load. the device provides an external driver capability for two external devices. fo r each external dr iver there are two control outputs availabl e: one output for contro lling the input and one ou tput for diagno sis enable input. the current sense output of the external smart power drivers can be connected to the is pin. the spoc - BTS5482SF provides a fail-safe feature via limp home input pin. the power transistors are built by n-channel vertical power mosfets with charge pumps. protective functions ? reverse battery protecti on with external components ? reversave tm - reverse battery protection by self turn-on of channels 0, 1, 2 and 3 ? short circuit protection ? over load protection ? thermal shutdown with latch an d dynamic temperature protection ? over current tripping ? over voltage protection ? loss of ground protection ? electrostatic discha rge protection (esd) diagnostic functions ? multiplexed proportional load current sense signal (is) ? enable function for current s ense signal configurable via spi ? high accuracy of current sense signal at wide load current range ? current sense ratio ( k ilis ) configurable for leds or bulbs for channel 2 and 3 ? very fast diagnosis in led mode ? feedback on over temperature and over load via spi ? multiplexed switch bypass monitor provides short circuit to v s detection ? integrated, in two steps programmable current source for open load in off-state detection application specific functions ? fail-safe activation via lhi pin ? control of two additional loads with external smart power switches applications ? high-side power switch for 12 v grounded loads in automotive applications ? especially designed for standard exterior lighting like high beam, low beam, indicator, parking light and equivalent led modules. ? load type configuration via spi (bulbs or leds) for optimized load control ? replaces electromechanical relays, fuses and discrete circuits
data sheet 6 rev. 1.0, 2013-06-05 spoc - BTS5482SF block diagram 2blockdiagram figure 1 block diagram spoc - BTS5482SF limp home control led mode control external driver control 3 2 1 channel 0 power supply driver logic gate control & charge pump clamp for inductive load over current protection load current sense temperature sensor esd protection gnd spi current sense multiplexer so sclk si cs switch bypass monitor vs out3 out2 out1 out0 in2 in3 in1 edo0 edd0 edo1 edd1 esd protection lhi is vdd overview _std_ext.emf
spoc - BTS5482SF block diagram data sheet 7 rev. 1.0, 2013-06-05 2.1 terms figure 2 shows all terms used in this data sheet. figure 2 terms in all tables of electrical characteri stics is valid: channel related symbols without channel number are valid for each channel separately (e.g. v ds specification is valid for v ds0 ? v ds3 ). all spi register bits are marked as follows: addr.parameter (e.g. hwcr.cl ). in spi register description, the values in bold letters (e.g. 0 ) are default values. i dd v dd v so v in 2 i si v in 3 i cs v s i is i s vdd s0 si cs is vs v si v cs v sc l k v in 1 i in 1 in1 in2 i sc l k sclk v is i in 3 in3 gnd i gnd v lhi i lhi lhi out0 i l0 out1 edo 0 edd1 i l1 i edd1 out2 i l2 out3 i l3 v out3 v out2 v ds3 v ds2 v out1 v out0 v ds1 v ds0 v edd1 v ed o 0 edo 1 edd0 i ed o 1 i edd0 i ed o 0 v ed o 1 v edd0 i so i in 2 te rm s_std _ext . e m f
data sheet 8 rev. 1.0, 2013-06-05 spoc - BTS5482SF pin configuration 3 pin configuration 3.1 pin assignment spoc - BTS5482SF figure 3 pin configuration pg-dso-36-43 (top view ) out1 out2 out2 vs 36 35 34 33 32 31 1 2 3 4 5 6 7 8 30 29 vs out1 out1 out1 28 27 26 25 24 23 9 10 11 12 13 14 15 16 22 21 edd0 edo1 edd1 gnd 18 19 20 17 in3 out0 out0 out0 out0 in1 in2 vs vs gnd lhi cs sclk si out3 out3 vs edo0 vs n.c. vdd n.c. so is
spoc - BTS5482SF pin configuration data sheet 9 rev. 1.0, 2013-06-05 3.2 pin definitions and functions pin symbol i/o function power supply pins 1, 2, 9, 28, 35, 36 1) 1) all vs pins have to be connected. vs ? positive power supply for high-side power switch 19 vdd ? logic supply (5 v) 15, 22 gnd ? ground connection parallel input pins (integrated pull -down, leave unused pins unconnected) 16 in1 i input signal of channel 1 (high active) 17 in2 i input signal of channel 2 (high active) 18 in3 i input signal of channel 3 (high active) power output pins 3, 4, 5, 6 2) 2) all outputs pins of each channel have to be connected. out0 o protected high-side power output of channel 0 31, 32, 33, 34 2) out1 o protected high-side power output of channel 1 29, 30 2) out2 o protected high-side power output of channel 2 7, 8 2) out3 o protected high-side power output of channel 3 spi & diagnosis pins 14 cs i chip select of spi interface (low active); integrated pull up 13 sclk i serial clock of spi interface 12 si i serial input of spi interface (high active) 11 so o serial output of spi interface 21 is o current sense output signal limp home pin (integrated pull-down, pull-down resistor recommended) 10 lhi i limp home activation signal (high active) external driver pins (integrated pull-down, leave unused external driver pins unconnected) 26 edo0 o external driver output for activation of external driver 0 24 edo1 o external driver output for activation of external driver 1 25 edd0 o external driver diagnosis enable signal of external driver 0 23 edd1 o external driver diagnosis enable signal of external driver 1 not connected pins 20, 27 n.c. ? not connected, internally not bonded
data sheet 10 rev. 1.0, 2013-06-05 spoc - BTS5482SF electrical characteristics 4 electrical characteristics 4.1 absolute maximum ratings absolute maximum ratings 1) t j = -40 to +150 c; all voltages with respect to ground (unless otherwise specified) pos. parameter symbol limit values unit conditions min. max. supply voltage 4.1.1 power supply voltage v s -0.3 28 v ? 4.1.2 logic supply voltage v dd -0.3 5.5 v ? 4.1.3 reverse polarity voltage according figure 31 -v bat(rev) ?16v t jstart = 25 c t 2min. 2) 4.1.4 supply voltage for short circuit protection (single pulse) v s(sc) v r ecu = 20 m ? l = 0 or 5 m 3) channel 0, 1 0 24 r cable = 6 m ? /m l cable = 1 h/m channel 2, 3 0 24 r cable = 16 m ? /m l cable = 1 h/m 4.1.5 supply voltage for lo ad dump protection with connected loads v s(ld) ?40v r i = 2 ? 4) t = 400 ms 4.1.6 current through ground pin i gnd ?25ma t 2min. 4.1.7 current through vdd pin i dd -25 12 ma t 2min. power stages 4.1.8 load current i l ? 5) i l(htrip) a 6) 4.1.9 maximum energy dissipation single pulse e as mj 7) t j(0) = 150 c channel 0, 1 ? 180 i l(0) = 5 a channel 2, 3 ? 45 i l(0) = 2 a 4.1.10 thermal latch restart time t delay(cl) 50 ? ms diagnosis pin 4.1.11 current through sense pin is i is -8 8 ma t 2min. input pins 4.1.12 voltage at input pins v in -0.3 5.5 v ? 4.1.13 current through input pins i in -0.75 -2.0 0.75 2.0 ma ? t 2min. spi pins 4.1.14 voltage at chip select pin v cs -0.3 v dd + 0.3 v ? 4.1.15 current through chip select pin i cs -2.0 2.0 ma t 2min. 4.1.16 voltage at serial input pin v si -0.3 v dd + 0.3 v ? 4.1.17 current through serial input pin i si -2.0 2.0 ma t 2min. 4.1.18 voltage at serial clock pin v sclk -0.3 v dd + 0.3 v ? 4.1.19 current through serial clock pin i sclk -2.0 2.0 ma t 2min.
spoc - BTS5482SF electrical characteristics data sheet 11 rev. 1.0, 2013-06-05 note: stresses above the ones listed here may cause perm anent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note: integrated protection functions are designed to prevent ic destruction under fault conditions described in the data sheet. fault conditions are considered as ?outside? normal operating range. protection functions are not designed for continuous repetitive operation. 4.1.20 voltage at serial output pin v so -0.3 v dd + 0.3 v ? 4.1.21 current through serial output pin i so -2.0 2.0 ma t 2min. limp home pin 4.1.22 voltage at limp home input pin v lhi -0.3 5.5 v ? 4.1.23 current through limp home input pin i lhi -0.75 -2.0 0.75 2.0 ma ? t 2min. external driver pins 4.1.24 voltage at external driver output v edo -0.3 v dd + 0.3 v ? 4.1.25 current through ex ternal driver output i edo -1.0 1.0 ma t 2min. 4.1.26 voltage at external driver diagnosis enable v edd -0.3 v dd + 0.3 v ? 4.1.27 current through extern al driver diagnosis enable i edd -1.0 1.0 ma t 2min. temperatures 4.1.28 junction temperature t j -40 150 c? 4.1.29 dynamic temperature increase while switching ? t j ?60k? 4.1.30 storage temperature t stg -55 150 c? esd susceptibility 4.1.31 esd susceptibility hbm out pins vs. vs other pins incl. out vs. gnd v esd -4 -2 4 2 kv hbm 8) ? ? 1) not subject to production test, specified by design. 2) device is mounted on an fr4 2s2p board according to jedec jesd51-2,-5,-7 at natu ral convection; the product (chip+package) was simulated on a 76.4 x 114.3 x 1.5 mm board wi th 2 inner copper layers (2 x 70 m cu, 2 x 35 m cu). where applicable, a thermal via array under the pa ckage contacted the first inner copper layer. 3) in accordance to aec q100-012 and aec q101-006. 4) r i is the internal resistance of the load dump pulse generator. 5) no protection mechanism available. inverse current needs to be limited by external ci rcuitry to prevent overheating. 6) over current protection is an integrated protection function. 7) pulse shape represents inductive switch off: i d(t) = i d (0) (1 - t / t pulse ); 0 < t < t pulse 8) esd resistivity, hbm according to ansi/esda/je dec js-001-2010 absolute maximum ratings (cont?d) 1) t j = -40 to +150 c; all voltages with respect to ground (unless otherwise specified) pos. parameter symbol limit values unit conditions min. max.
data sheet 12 rev. 1.0, 2013-06-05 spoc - BTS5482SF electrical characteristics 4.2 thermal resistance note: this thermal data was generated in accordance wit h jedec jesd51 standards. fo r more information, go to www.jedec.org . pos. parameter symbol limit values unit conditions min. typ. max. 4.2.1 junction to soldering point 1) 1) not subject to production test, specified by design. r thjsp ? ? 20 k/w measured to pin 1, 2, 9, 28, 35, 36 4.2.2 junction to ambient 1) r thja ?35?k/w 2) 2) specified r thja values is according to jedec jesd51-2,-5,-7 at natural convection on fr4 2s2p board; the product (chip+package) was simulated on a 76.4 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70 m cu, 2 x 35 m cu). where applicable, a thermal via array under the package contacted the first inner copper layer.
spoc - BTS5482SF power supply data sheet 13 rev. 1.0, 2013-06-05 5 power supply the spoc - BTS5482SF is supplied by two supply voltages v s and v dd . the v s supply line is used by the power switches. the v dd supply line is used by the spi related circuitr y and for driving the so line. a capacitor between pins vdd and gnd is recommended as shown in figure 31 . there is a power-on reset function implemented for the v dd logic power supply. after start-up of the logic power supply, all spi registers are reset to their default values. the spi interface including da isy chain function is active as soon as v dd is provided in the specified range independent of v s . first spi data are the output register values for internal channels with ter = 1. specified parameters are valid for the supply voltage range according v s(nor) or otherwise specified. for the extended supply voltage range according v s(ext) device functionality (switching, diagnosis and protection functions) are still given, parameter deviations are possible. 5.1 power supply modes the following table shows all possible power supply modes for v s , v dd and the pin lhi. 5.1.1 stand-by mode and device wake-up mechanisms stand-by mode is entered as soon as the current sense multiplexer ( dcr.mux ) is in default (stand-by) position and all input pins are not set. all error latches are clear ed automatically in stand-by mode. as soon as stand-by mode is entered, register hwcr.stb is set. to wake-up the device, the current sense multiplexer ( dcr.mux ) is programmed different to default (stand-by) position. the power-on wake up time t wu(po) has to be considered. idle mode parameters are valid, when all channels are swit ched off, whereas the current sense multiplexer is not in default position, and v dd supply is available. note: a transition from operation to stand-by mode does not reset the spi registers. so, if v dd is present and spi is programmed, a changing to mux = 111 b does not reset the spi registers. an activation of the channels via the input pin inx will wake up the devic e with the former spi register settings. power supply modes off off spi on reset off on via inx limp home mode without spi normal operation limp home mode with spi 1) 1) spi read only v s 0v 0v 0v 0v 13.5v 13.5v 13.5v 13.5v 13.5v v dd 0v 0v 5v 5v 0v 0v 0v 5v 5v lhi 0v5v0v5v0v 0v 5v 0v 5v power stage, protection ? ? ? ? ? ? 2) 2) channel 1, 2 and/or 3 activated according to the state of inx ? 2) ?? 2) limp home ? ? ? ? ? ? ? ? ? spi (logic) ? ? ?? reset reset reset ? reset 3) 3) spi reset only with applied v s voltage stand-by current ? ? ? ? ?? 4) 4) when inx = 0 v ? ? 5) 5) when dcr.mux = 111 b and inx = 0 v ? idle current ? ? ? ? ? ? ? ? 6) 6) when all channels are in off-state and dcr.mux 111 b ? diagnosis ? ? ? ? ? ? ? ?? 7) 7) current sense disabled in limp home mode
data sheet 14 rev. 1.0, 2013-06-05 spoc - BTS5482SF power supply activating one of the outputs via the input pi ns (inx = high) will wake-up the de vice out of stand-by mode. the power stages are working without vdd supply according to the table in chapter 5.1 . the output tu rn-on time will be extended by the stand-by channel wake up time t wu(stch) as long as no other channel is active. if one channel is active already before, channel turn-on times t on ( 6.6.12 ) can be considered. note: in the operation with v dd = 0 v and inx = high a switching off of a ll input signals will turn the device in stand- by mode. in stand-by mode the error latches are cleared. limp home (lhi = high) applied for a time longer than t lh(ac) will wake-up the device out of stand-by mode after the power-on wake up time t wu(po) and it is working without vdd supply. channels 1, 2 and 3 can be activated via the input pins inx. the error latches can be cleared by a low-high tr ansition at the according input pin. 5.2 reset there are several reset triggers implemented in the de vice. they reset the spi registers including the over temperature latches to their default values. the po wer stages will switch off, if they are activated via the spi register outl.n . if the power stages are activated via the parallel input pins they are not affected by the reset signals. the err-flags are cleared by those reset triggers. the over temperature protection and latches are functional after a reset trigger. note: during a reset only the channels 1, 2 and 3 can be activated via the according input pins. the input assigned mode is not available during a reset. the first spi transmission after any ki nd of reset contains at pin so the read information from the standard diagnosis, the transmission error bit ter is set. power-on reset the power-on reset is released, when v dd voltage level is higher than v dd(po) . the spi interface can be accessed after wake up time t wu(po) . if one of the parallel input pins inx or th e lhi pin is high, the power-on reset is not affecting the protection latches. reset command there is a reset command available to reset all register bi ts of the register bank an d the diagnosis registers. as soon as hwcr.rst = 1 b , a reset, equivalent to power-on reset is executed. the spi inte rface can be accessed after transfer delay time t cs(td) . limp home mode the limp home mode will be activate d as soon as the pin lhi is set to high for a time longer than t lh(ac) . the spi write-registers are reset with applied v s voltage and the protection latches are cleared. the outputs out1 to out3 can be activated via the input pins al so during activated limp home mode. the error latches can be cleared by a low-high transition at the according input pin. for application example see figure 31 . the spi interface is operating normally, so the limp home register bit lhi as well as the error flags can be read, but any write command will be ignored.
spoc - BTS5482SF power supply data sheet 15 rev. 1.0, 2013-06-05 5.3 electrical characteristics note: characteristics show the deviat ion of parameter at the given supp ly voltage and junction temperature. electrical characteristics power supply unless otherwise specified: v s = 8 v to 17 v, v dd = 3.0 v to 5.5 v, t j = -40 c to +150 c typical values: v s = 13.5 v, v dd = 4.3 v, t j = 25 c pos. parameter symbol limit values unit test conditions min. typ. max. 5.3.1 supply voltage range for normal operation power switch v s(nor) 8?17v? 5.3.2 extended supply volt age range for operation power switch v s(ext) 4.5 1) 1) load current sense diagnosis is not available for v s <6.0v ?28 2) 2) not subject to production test, specified by design. v parameter deviations possible 5.3.3 undervoltage shutdown v s(uv) ?3.7?v 5.3.4 stand-by current for whole device with loads i s(stb) ? ? ? ? 4.5 28 a v dd = 0 v v lhi = 0 v 2) t j = 25 c 2) t j 85 c 5.3.5 idle current for whole device with loads, all channels off i s(idle) ? 14.5 ? ma v dd = 5 v dcr.mux = 110 5.3.6 logic supply voltage v dd 3.0? 5.5v ? 5.3.7 logic supply current i dd ? ? 80 350 200 500 a 3) v lhi = 0 v v dd = 5 v v is = 0 v chip in idle f sclk = 0 hz v cs = 5 v f sclk = 5 mhz v cs = 0 v 3) device in normal operation without any temperature or overcurrent latches set 5.3.8 logic stand-by current i dd(stb) ?25?a v cs = v dd f sclk = 0 hz chip in stand-by 5.3.9 operating current for whole device active i gnd ?1521ma f sclk = 0 hz lhi input characteristics 5.3.10 l-input level at lhi pin v lhi(l) 0?0.8v? 5.3.11 h-input level at lhi pin v lhi(h) 1.8? 5.5v ? 5.3.12 l-input current through lhi pin i lhi(l) 3820a 2) v lhi = 0.6 v 5.3.13 h-input current through lhi pin i lhi(h) 10 40 80 a v lhi = 5 v reset 5.3.14 power-on reset threshold voltage v dd(po) ??2.4v? 5.3.15 power-on wake up time t wu(po) ??200s 2) 5.3.16 stand-by channel wake up time t wu(stch) ??200s 2) 5.3.17 limp home acknowledgement time t lh(ac) 5?200s 2)
data sheet 16 rev. 1.0, 2013-06-05 spoc - BTS5482SF power stages 6 power stages the high-side power stages are built by n-channel vert ical power mosfets (dmos) with charge pumps. there are four channels implemented in the device. 6.1 output on-state resistance the on-state resistance r ds(on) depends on the supply voltage v s as well as on the junction temperature t j . figure 4 shows those dependencies. the behavior in reverse polarity mode is described in section 7.6 . figure 4 typical on-state resistance 6.2 input circuit the outputs of the spoc - BTS5482SF can be activated either via the spi register outl.outn or via the dedicated input pins. there are two different ways to us e the input pins, the direct drive mode and the assigned drive mode. the default setting is the direct drive mode. to activate the assigned drive mode the register bit icr.incg needs to be set. additionally, there are two ways of usin g the input pins in combination with the outl register by programming the icr.col parameter. ? icr.col = 0 b : a channel is switched on either by the according outl register bit or the input pin. ? icr.col = 1 b : a channel is switched on by the according outl register bit only, when the respec tive input pin is high. in this configuration, a pwm signal can be applied to the inpu t pin and the channel is activated by the spi register outl . 0 10 20 30 40 50 60 70 80 -50 0 50 100 150 r ds(on) [m ] t j [c] v s = 13.5 v channel 0,1 (bulb) channel 2,3 (bulb) channel 2,3 (led) 0 10 20 30 40 50 60 70 80 0 5 10 15 20 25 30 r ds(on) [m ] v s [v] t j = 25 c channel 0, 1 (bulb) channel 2,3 (bulb) channel 2,3 (led)
spoc - BTS5482SF power stages data sheet 17 rev. 1.0, 2013-06-05 figure 5 shows the complete input switch matrix. figure 5 input switch matrix the current sink to ground ensures t hat the input signal is low in case of an open input pin. the zener diode protects the input circ uit against esd pulses. 6.2.1 input direct drive this mode is the default after the device?s wake up and reset. the input pins activate the channels during normal operation (with default setting of bit icr.incg ), stand-by mode and limp home mode. channel 0 and the external drivers can be activated only via the spi-bit outx.outn in direct drive mode. the inputs are linked directly to the channels according to: table 1 direct drive mode input pin assigned channel , if icr.incg = 0 b in1 channel 1 in2 channel 2 in3 channel 3 inputmatr ix_std_ext .emf in1 incg gate driver 2 gate driver 1 gate driver 0 gate driver 3 & or out2 out1 out0 out3 & or col in2 & or & or in3 or out4 out5 external driver output 0 & or external driver output 1 & or &
data sheet 18 rev. 1.0, 2013-06-05 spoc - BTS5482SF power stages 6.2.2 input assigned drive to activate the assigned drive function the register bit icr.incg needs to be set. in this mode all output channels can be activated via the input pins. ch annel 2, 3 and the two external drivers are assigned to only one input pin. the following mapping is used: 6.3 power stage output the power stages are built to be us ed in high side configuration ( figure 6 ). figure 6 power stage output the power dmos switches with a dedicated slope, which is optimized in terms of electromagnetic emission (eme). defined slew rates and edge shaping allow lowe st eme during pwm operation at low switching losses. 6.3.1 bulb and led mode channel 2 and channel 3 can be configured in bulb and led mode via the spi registers hwcr.ledn . during led mode following parameters are changed for an optimize d functionality with led loads: on-state resistance r ds(on) , switching timings ( t delay(on) , t delay(off) , t on , t off ), slew rates d v /d t on and d v /d t off , current protections i l(trip) and current sense ratio k ilis . table 2 assigned drive mode input pin assigned channel , if icr.incg = 1 b in1 channel 0 in2 channel 1 in3 channel 2, channel 3, external driver 0, external driver 1 output.emf out gnd v out vs v ds v bat
spoc - BTS5482SF power stages data sheet 19 rev. 1.0, 2013-06-05 6.3.2 switching resistive loads when switching resistive loads the following s witching times and slew rates can be considered. figure 7 switching a resistive load 6.3.3 switching inductive loads when switching off inductive loads wi th high-side switches, the voltage v out drops below ground potential, because the inductance intends to cont inue driving the current. to prevent the destruction of the device due to high voltages, there is a voltage clamp mechanism implem ented, which limits that nega tive output voltage to a certain level ( v ds(cl) ( 6.6.2 )). see figure 6 for details. the device provides smartclamp functionality. to increase the energy capability, the clamp voltage v ds(cl) increases with the junction temperature t j and load current i l . please refer also to section 7.7 . when switching inductive loads, it has to be ensured that the clamp mechanism of the device is not activated. 6.3.4 switching high inrush loads when switching loads with high inrush currents like e.g. hi gh capacitive loads, it has to be ensured that in normal operating range the maximum load current is below the current trip level of the device. if the current trip level is touched, the device would oper ate under fault conditions that are consid ered as outside normal operating range. in this case absolute maxi mum ratings are exceeded (see 4.1.8 ). please refer to section 4 and section 7 for further information. 6.4 inverse current behavior during inverse currents ( v out > v s ) the affected channel stays in on- or in off-state. furthermore, during applied inverse currents no err-flag is set. the functionality of unaffected channel s is not influenced by inverse currents applied to other channels (except effects due to junction temperature increase). influences on the diagnostic function of unaffected channels are possible only for the current sense ratio, please refer to ? k ilis(ic) ( 8.5.3 ). note: no protection mechanism like temperature protection or current protection is active during applied inverse currents. inverse currents cause power losses inside the dmos, which increase the overall device temperature, which could lead to a switch off of the unaffected channels due to over temperature. v out t swit ch on . e m f t on t off t 90% of v s 10% of v s 70% of v s d v / d t on 30% of v s 70% d v / d t off 30% t delay(on) t delay(off) in / outx t on(rise) t off (fall )
data sheet 20 rev. 1.0, 2013-06-05 spoc - BTS5482SF power stages 6.5 external driver control two external smart power drivers can be driven by t he spoc - BTS5482SF via the external driver control block. for each external driver there are tw o control outputs available: one out put for controlling the input (edox) and one output for diagnosis enable input (eddx). the curren t sense output of the external smart power drivers can be connected to the is pin. for details please refer to figure 31 . the external driver outputs can be used only with applied v dd voltage. the external driver outputs are internally pulled down. the external drivers can be activated via spi-bits outh.out4 and outh.out5 or via the input pin in3 in assigned drive mode. the external drivers? diagnos tic enable signals can be activated via the spi register dcr.mux . for being compliant to profet+ diagnostic functions, it is possible to configure pin edd0 as den and edd1 as dsel. therefore, the bit outh.pro+ needs to be set. the dsel will be set in accordance to the multiplexer setting dcr.mux . note: the usable duty cycle range and diagnostic timings fo r the external drivers depend on the external driver?s characteristics. table 3 profet+ compliancy mux setting dcr.mux edd0 used as den edd1 used as dsel 100 b 10 101 b 11
spoc - BTS5482SF power stages data sheet 21 rev. 1.0, 2013-06-05 6.6 electrical characteristics electrical characteristics power stages unless otherwise specified: v s = 8 v to 17 v, v dd = 3.0 v to 5.5 v, t j = -40 c to +150 c typical values: v s = 13.5 v, v dd = 4.3 v, t j = 25 c pos. parameter symbol limit values unit test conditions min. typ. max. output characteristics 6.6.1 on-state resistance r ds(on) m ? channel 0, 1 ? ? 4 6 ? 8.5 i l = 7.5 a 1) t j = 25 c t j = 150 c channel 2, 3 ? ? ? ? 15 21 45 70 ? 28 ? 100 hwcr.ledn = 0 i l = 2.6 a 1) t j = 25 c t j = 150 c hwcr.ledn = 1 i l = 0.6 a 1) t j = 25 c t j = 150 c 6.6.2 output clamp v ds(cl) v channel 0, 1 32 40 ? ? 54 55 t j = 25 c i l = 20 ma 1) t j = 150 c i l = 6 a channel 2, 3 32 40 ? ? 54 55 t j = 25 c i l = 20 ma 1) t j = 150 c i l = 2 a 6.6.3 output leakage current per channel in stand-by i l(offstb) a outl.outn = 0 dcr.mux = 111 channel 0, 1 ? ? ? ? ? ? 2 10 50 t j = 25 c 1) t j = 85 c 1) t j = 105 c channel 2, 3 ? ? ? ? ? ? 1 4 20 t j = 25 c 1) t j = 85 c 1) t j = 105 c 6.6.4 output leakage current per channel in idle mode i l(offidle) a outl.outn = 0 dcr.mux 111 channel 0, 1 ? ? ? ? ? ? 60 80 530 1) t j = 85 c 1) t j = 105 c t j = 150 c channel 2, 3 ? ? ? ? ? ? 45 50 230 1) t j = 85 c 1) t j = 105 c t j = 150 c
data sheet 22 rev. 1.0, 2013-06-05 spoc - BTS5482SF power stages 6.6.5 inverse current capability per channel -i l(ic) a 1) no influences on switching functionality of unaffected channels, k ilis influence according ? k ilis(ic) ( 8.5.3 ) channel 0, 1 6 ? ? channel 2, 3 2 ? ? input characteristics 6.6.6 l-input level v in(l) 0?0.8v? 6.6.7 h-input level v in(h) 1.8 ? 5.5 v ? 6.6.8 l-input current i in(l) 3820a 1) v in = 0.6 v dcr.mux 111 6.6.9 h-input current i in(h) 10 40 80 a v in = 5 v electrical characteristics power stages (cont?d) unless otherwise specified: v s = 8 v to 17 v, v dd = 3.0 v to 5.5 v, t j = -40 c to +150 c typical values: v s = 13.5 v, v dd = 4.3 v, t j = 25 c pos. parameter symbol limit values unit test conditions min. typ. max.
spoc - BTS5482SF power stages data sheet 23 rev. 1.0, 2013-06-05 timings 6.6.10 turn-on delay to 10% v s t delay(on) s 1) v s = 13.5 v channel 0, 1 ? 35 ? ? channel 2, 3 ? ? 25 8 ? ? hwcr.ledn = 0 hwcr.ledn = 1 6.6.11 turn-off delay to 90% v s t delay(off) s 1) v s = 13.5 v channel 0, 1 ? 45 ? ? channel 2, 3 ? ? 30 10 ? ? hwcr.ledn = 0 hwcr.ledn = 1 6.6.12 turn-on time to 90% v s including turn-on delay t on s v s = 13.5 v dcr.mux 111 channel 0, 1 ? ? 100 r l = 2.2 ? channel 2, 3 ? ? ? ? 100 50 hwcr.ledn = 0 r l = 6.8 ? hwcr.ledn = 1 r l = 33 ? 6.6.13 turn-off time to 10% v s including turn-off delay t off s v s = 13.5 v channel 0, 1 ? ? 150 r l = 2.2 ? channel 2, 3 ? ? ? ? 110 50 hwcr.ledn = 0 r l = 6.8 ? hwcr.ledn = 1 r l = 33 ? 6.6.14 turn-on rise time from 10% to 90% v s t on(rise) s v s = 13.5 v dcr.mux 111 channel 0, 1 ? ? 45 r l = 2.2 ? channel 2, 3 ? ? ? ? 40 11 hwcr.ledn = 0 r l = 6.8 ? hwcr.ledn = 1 r l = 33 ? 6.6.15 turn-off fall time from 90% to 10% v s t off(fall) s v s = 13.5 v channel 0, 1 ? ? 45 r l = 2.2 ? channel 2, 3 ? ? ? ? 40 11 hwcr.ledn = 0 r l = 6.8 ? hwcr.ledn = 1 r l = 33 ? electrical characteristics power stages (cont?d) unless otherwise specified: v s = 8 v to 17 v, v dd = 3.0 v to 5.5 v, t j = -40 c to +150 c typical values: v s = 13.5 v, v dd = 4.3 v, t j = 25 c pos. parameter symbol limit values unit test conditions min. typ. max.
data sheet 24 rev. 1.0, 2013-06-05 spoc - BTS5482SF power stages 6.6.16 turn-on/off matching | t on - t off | s v s = 13.5 v channel 0, 1 ? ? 90 r l = 2.2 ? channel 2, 3 ? ? ? ? 70 50 hwcr.ledn = 0 r l = 6.8 ? hwcr.ledn = 1 r l = 33 ? 6.6.17 turn-on slew rate 30% to 70% v s d v / d t on v/s v s = 13.5 v channel 0, 1 ? 0.7 2.0 r l = 2.2 ? channel 2, 3 ? ? 0.9 2.5 2.5 6.0 hwcr.ledn = 0 r l = 6.8 ? hwcr.ledn = 1 r l = 33 ? 6.6.18 turn-off slew rate 70% to 30% v s -d v / d t off v/s v s = 13.5 v channel 0, 1 ? 0.7 2.0 r l = 2.2 ? channel 2, 3 ? ? 0.9 2.5 2.5 6.0 hwcr.ledn = 0 r l = 6.8 ? hwcr.ledn = 1 r l = 33 ? external driver control 6.6.19 l level external driver output voltage v edo(l) 0?0.4v i edo = -0.5 ma 6.6.20 h level external driver output voltage v edo(h) v dd - 0.4v ? v dd v i edo = 0.5 ma v dd = 4.3 v 6.6.21 external driver output enable time t edo(en) ??4 s 1) c l = 20 pf 6.6.22 external driver output disable time t edo(dis) ??4 s 1) c l = 20 pf 6.6.23 l level external driver diagnosis enable voltage v edd(l) 0?0.4v i edd = -0.5 ma 6.6.24 h level external driver diagnosis enable voltage v edd(h) v dd - 0.4v ? v dd v i edd = 0.5 ma v dd = 4.3 v 6.6.25 external driver diagnosis enable enable time t edd(en) ??4 s 1) c l = 20 pf 6.6.26 external driver diagnosis enable disable time t edd(dis) ??4 s 1) c l = 20 pf 1) not subject to production test, specified by design. electrical characteristics power stages (cont?d) unless otherwise specified: v s = 8 v to 17 v, v dd = 3.0 v to 5.5 v, t j = -40 c to +150 c typical values: v s = 13.5 v, v dd = 4.3 v, t j = 25 c pos. parameter symbol limit values unit test conditions min. typ. max.
spoc - BTS5482SF protection functions data sheet 25 rev. 1.0, 2013-06-05 7 protection functions spoc - BTS5482SF provides embedded protective functions, which are designed to prevent ic destruction under fault conditions described in this da ta sheet. fault conditions are considered as ?outside? normal operating range. protective functions are neither designed for continuous nor for repetitive operation. to provide high switching capability and robustness , the device is manage d by a state machine ( figure 8 ). figure 8 BTS5482SF state diagram each internal channel of BTS5482SF has its own state machine to manage the protection mechanisms. device is starting-up in inrush state and depending on different conditions it will change to oper ative state (nor mal condition) or to fault state (overload condition). 7.1 inrush state after start-up the device enters inrush state providing high current trip level i l(htrip) ( 7.10.1 ) with a limited number of retries (see figure 11 ). after the respective channel is in on-state for t > t delay(ltrip) ( 7.10.2 ), the channel changes to operative state (see chapter 7.2 ). in case the channels are driven in pwm (pulse width modulation) the on- time is cumulated until t delay(ltrip) is reached. for a detailed description of the timers see chapter 7.4 . if a latch off condition occurs, the device will change to fault state (see chapter 7.3 ). 7.1.1 over current protec tion in inrush state the maximum load current i l is switched off in case of exce eding the over current trip level i l(htrip) by the device itself. depending on the total short circuit impedance high er current over shoots may occur. a limited auto-restart function is implemented. please re fer to following fi gures for details. fault operative i l( l tr i p ) , no retries inrush i l(htrip) , n retry ot /dt or oc hwcr .cl =1 b & timerinrush expired or v s < v s(u v) (*) or lhi & timerinrush expired hwcr. cl=1 b or lhi startup ot /dt or oc w ith or oc at state_diagram.emf legend: ot ... over temperature event dt ... dynamic temperature event oc ... o v e r c u r r e n t e v e n t timerinrush expired or v s < v s(uv) (*) timeron expired (**) (**) v ds(vtrip) n re try (*) inrus h s tate with (**) itc x bit and timerinrus h will be c leared i l( l t r i p )
data sheet 26 rev. 1.0, 2013-06-05 spoc - BTS5482SF protection functions figure 9 over current protection with latch due to reaching maximum number of retries n retry in pwm operation the number of retries is cumulated over pwm cycles until n retry is reached. please refer to figure 10 for a more detailed view. figure 10 over current protection with latch due to reaching maximum number of retries n retry in pwm operative inrush fault i l i is t t t err t currenttripping_nretry.emf cl = 1 v ds t v ds(vtrip ) i l( h tr i p ) over current in / outx t t j t j(start) n = 1 over load removed t j(sc ) n= n retry * err-flag will be reset by standard diagnosis readout during restart * switch off by over current detection latch off due to n retry(lv) t j(sc) - ? t j normal operation fault fault inrush fault i l t t err t currenttripping_nretry_pwm .emf cl = 1 i l(htrip) in / outx * err-flag will be reset by standard diagnosis readout during restart * i l(ltrip) n retry cl = 1 startup inrush operative operative t t delay(htrip) latch off due to i l(ltrip) switch off by over current detection latch off due to n retry (lv ) latch off due to n retry (lv ) 12 3 4 03132 1234 06789 53132
spoc - BTS5482SF protection functions data sheet 27 rev. 1.0, 2013-06-05 the err-flag will be set during over current shut down. it can be reset by reading the err-flag, unless fault state is reached by exceeding n retry . it will be set again with the next ov er current event. see figures above. the number of restarts n retry is depending on the v ds voltage according to the following figure and chapter 7.1.2 . figure 11 number of retries and trip levels dependent of v ds the retry latch is cleared by spi command hwcr.cl = 1 b . if the input pin or the bit in the spi register outl is still set, the channel will be turned- on immediately af ter the command hwcr.cl = 1 b . to prevent degradation of the device, channel is rest arting in operative state ( chapter 7.2 ). 7.1.2 over current protection at high v ds the spoc - BTS5482SF provides an over current protection at high v ds ( 7.10.6 ). for v ds > v ds(vtrip) and i l > i l(vtrip) during turn-on the channel switches off and latches immediately. for details pl ease refer to parameter i l(vtrip) ( 7.10.5 ). the current trip level i l(vtrip) is below the cu rrent trip level i l(htrip) at v ds =7v. the over current latch is cleared by spi command hwcr.cl = 1 b . if the input pin or the bit in the spi register outl is still set, the channel will be tur ned-on immediately after the command hwcr.cl = 1 b . to prevent degradation of the device it is recommended to wait t delay(cl) ( 4.1.10 ) until resetting the latch and restarting in operative state. figure 12 over current protection in case of high v ds voltages i l i l(htrip) v ds 5 10 15 20 i l(vtrip) n= n retry(lv) n= n retry(mv) no r etr y currenttrippingvsvds.emf inrush fault operative i l i is t t t err t currenttrippinghighvds.emf cl = 1 v ds t v ds(vtrip) i l(vtrip) high v ds over current normal operation over load removed in / outx
data sheet 28 rev. 1.0, 2013-06-05 spoc - BTS5482SF protection functions 7.1.3 over temper ature protection each channel has its own temperature sensor. if the te mperature at the channel exceeds the thermal shutdown temperature t j(sc) , the channel will switch off and latch to prev ent destruction (also in case of v dd = 0v). after an overcurrent event the threshold t j(sc) will be decreased by th e thermal hysteresis ? t j ( 7.10.11 ). in order to reactivate the channel, the temperature must drop by at least th e thermal hysteresis ? t j and the over temperature latch must be cleared by spi command hwcr.cl = 1 b . when channel restarts the overtemperature threshold is reset to t j(sc) . if the input pin or the bit in the spi register outl is still set, the channel w ill be turned-o n immediately after the command hwcr.cl = 1 b .to prevent degradation of the de vice it is recommended to wait t delay(cl) ( 4.1.10 ) until resetting the latch and restarting in operative state. figure 13 over current protection with latch due to reaching over temperature t j(sc) inrush fault operative i l i is t t t err t currenttrippingdeltat_ot.emf cl = 1 v ds t v ds(vtrip ) i l(htrip ) over current normal operation in / outx t t j t j(sc) - ? t j t j(s tart) over load removed t j(sc ) * err-flag will be reset by standard diagnosis readout during restart * switch off by over current detection latch off due to over temperature n = 1 n < n retry
spoc - BTS5482SF protection functions data sheet 29 rev. 1.0, 2013-06-05 figure 14 shut down by over temperature oper. fault fault fault operative inrush i l i is t t t err t overload.emf cl = 1 in / outx cl = 1 i l(htrip) t t j t j(s tart) t j(sc ) latch off due to over temperature i l(ltrip) latch off due to over current t < t delay (htrip )
data sheet 30 rev. 1.0, 2013-06-05 spoc - BTS5482SF protection functions 7.1.4 dynamic temperature protection additionally, each channel has its own dynamic temperat ure protection to improve short circuit robustness when channels are doing automatic retries. the dynamic temperatur e protection will check th e junction temperature of each channel after an overcurrent event. when the junction temperature ( t j ) compared to the temperature of the reference sensor ( t ref ) is below the dynamic temperature threshold ? t j(res) the channel is restarting ( t 1 in figure 15 ). as soon as t j > t ref + ? t j(res) the channel will be latched off and the err-flag will be set ( t 2 in figure 15 ). the latch is cleared by spi command hwcr.cl = 1 b . if the input pin or the bit in the spi register outl is still set, the channel will be tur ned-on immediately after the command hwcr.cl = 1 b . to prevent degradation of the device it is recommended to wait t delay(cl) ( 4.1.10 ) until resetting the latch and restarting in operative state. figure 15 dynamic temperature protection with latch inrush operative fault i l t t err t dynamict_latch.emf cl = 1 i l(htrip ) over load normal operation in / outx t t t ref(1) + ? t j(res) over load removed t j(sc ) * t ref(2) + ? t j(res) latch off due to dynamic temperature protection dynamic temperature protection allows restart t ref t j t 1 t 2 * err-flag will be reset by standard diagnosis readout during restart
spoc - BTS5482SF protection functions data sheet 31 rev. 1.0, 2013-06-05 7.2 operative state in this state the device allows only low current trip level i l(ltrip) ( 7.10.4 ). channel switches off and latches immediately in case the trip level is reached. to change from operative state to inrush state the respective channel has to be in off-state for t delay(htrip) . for a detailed description see chapter 7.4 . 7.2.1 over current protec tion in operative state in case of a short circuit to gnd event with i l > i l(ltrip) ( 7.10.4 ), the channel is latched off immediately and it will change to fault state. for more details, please refer to the figure figure 16 . the over current latch is cleared by spi command hwcr.cl = 1 b . if the input pin or the bit in the spi register outl is still set, the channel will be turn ed-on immediately after the command hwcr.cl = 1 b . depending on the state of the timerinrush ( t delay(htrip) ) the device will either restart in inrush or operative state. figure 16 shut down by over current in operative state 7.2.2 over temperature prot ection in operative state if the junction temperature exceed s the thermal shutdown temperature t j(sc) , the channel will switch off and latch to prevent destruction (also in case of v dd = 0v). in order to reactivate the channel, the temperature must drop below t j(sc) and the over temperature latch must be cleared by spi command hwcr.cl = 1 b . if the input pin or the bit in the spi register outl is still set, the channel will be turned-on im mediately afte r the command hwcr.cl = 1 b .to prevent degradation of the device it is recommended to wait t delay(cl) ( 4.1.10 ) until resetting the latch and restarting in operative state. see figure 14 for a detailed view. 7.2.3 dynamic temperature pr otection in operative state in this state the dynamic temperatur e protection is not needed to protect the device. for an improved emi performance this function is disabled. 7.3 fault state in this state the respective channel is in a latched off condition due to an overload event occurred in inrush or operative state. to reactivate the channel the command hwcr.cl = 1 b has to be sent over spi. after the clear latch command the channel will ch ange to operative state. to restart in inrush state the respective channel has to be off for t > t delay(htrip) . see figure 16 and chapter 7.4 for further details. operative inrush fault inrush operative i l i is t t t err t currenttrippinglowvds.emf cl = 1 i l(htrip) over load removed in / outx t t delay (ltrip ) i l(ltrip) t t delay (htrip ) over load t t delay (ltri p )
data sheet 32 rev. 1.0, 2013-06-05 spoc - BTS5482SF protection functions 7.4 timers and n retry counter each state machine uses two different timers (timeron and timerinrush) to control the state transitions. a counter is used to limit the maximum number of automatic restarts ( n retry ). the timeron controls the automatic state transition from inrush to operative. as soon the channel is activated in inrush state (spi or in) the timeron ( 7.10.2 ) is running. the behavior of this timer is shown in the table below. in case of an overload event the timeron is reset to prov ide a higher in rush capability. figure 17 shows the timeron behavior when switching on a high inrush load. after the last overcurrent event the timeron is restarted. when the timer expires ( t > t delay(ltrip) ) the operative state is entered. figure 17 timer-on behavior with high inrush load in case of pwm operation the timeron is cumulating the on-state time of the channel. as soon as ? t on > t delay(ltrip) the channel is entering operative state. figure 18 shows a high ohmic short circuit in pwm operation, where the load current does not reach i l(htrip) . when ? t on > t delay(ltrip) the operative state is entere d. due to the lower current trip level i l(ltrip) the channel is latched off and the fault state is entered. table 4 timeron behavior timeron oc / dt / ot = 0 oc / dt / ot = 1 on = 0 on = 1 on = 0 on = 1 inrush state hold running n.a. reset operative / fault state reset reset reset reset inrush fault 0 1 2 oper. fault oper. inrush latch off due to n retry (lv ) i l t t err t timeron_inrush.emf i l(htrip) in / outx * err- flag will be rese t by stand ard diagnosis readout during restart i l(ltrip) n retry cl = 1 startup * t t delay (ltrip ) fault cl = 1 operative t t delay (htrip ) latch off due to i l(ltrip) switch off by over current detection 3 4 5 31 32 0 1 2
spoc - BTS5482SF protection functions data sheet 33 rev. 1.0, 2013-06-05 figure 18 timeron and timerinrush behavior in high ohmic short condition to reactivate the channel in operative state the command hwcr.cl = 1 b has to be sent. in case the device needs to be restarted in inrush state th e timerinrush has to be expired. see figure 18 . table 5 shows the behavior of the timerinrush in the di fferent states of the state machine. timerinrush is needed to change from operative or fault to inrush state. in standard configuration (itcx = 0) the timerinrush is only running when the respective channel is de activated. to provide some more flexibility in software, it is possible to have the timerinrush runn ing when the channel is activated or in pwm operation (itcx = 1). when limp home mode is activated the ti merinrush is running independent of the state of the channels. the bit itcx and timerinrush are reset at every state transition fr om inrush to operative or inrush to fault. see figure 8 . to limit the number of automatic retries each channel has its own retry counter. as so on the counter reaches the maximum value ( n retry ), the device changes to fault state. the value of this counter is frozen when the channel is switched off for t < t delay(htrip) . the behavior of this counter is shown in table 6 . table 5 timerinrush timerinrush itcx = 0 itcx = 1 on = 0 on = 1 on = 0 on = 1 inrush state running reset running reset operative / fault state running reset running running table 6 n retry counter n retry counter timerinrush not expired timerinrush expired on = 0 on = 1 on = 0 on = 1 inrush state frozen running reset n.a. operative / fault state reset reset reset reset inrush oper. fault inrush i l t t err t timeron_high_ohmic_short.emf i l(htrip) in / outx i l(ltrip) cl = 1 startup t delay(htrip) t on t delay(ltrip) itcx = 1 latch off due to i l(ltrip ) t on t on t delay(ltrip) t on
data sheet 34 rev. 1.0, 2013-06-05 spoc - BTS5482SF protection functions 7.5 undervoltage restarts to increase the device robustness at low v s condition, the device provides v s monitoring functionality. in case v s < v s(mon) the load current trip level is reduced to i l(ltrip) . in case i l > i l(ltrip) the channel will re start until the maximum number of retries ( n retry(lv) ) is reached. it has to be ensured that v s does not drop below v s(ext) , otherwise the undervoltage shutdown could be entered (see 5.3.3 ). if this occurs before curr ent trip level is reached, the protection mechanisms are reset and the channel s are restarting with lo w current trip level i l(ltrip) . if this occurs after over current detection (e.g. d ue to oscillations on batter y) the protection mechanisms are reset and the channels are restarting with high current trip level i l(htrip) . to mitigate oscillations on the battery a good filtering on vs is recommended. figure 19 behavior of current trip level in vs undervoltage condition 7.6 reverse polarity protection to reduce power losses during reverse polarity reversave tm functionality is implemented for all internal channels. they are turned-on to almost forward condition in reverse polarity condition, see parameter r ds(rev) . in reverse polarity mode, power dissipation is caused by the reverse on-state resistance r ds(rev) of each channel as well as each esd diode of the logic pins. the reverse current through the channels has to be limited by the connected loads. the current through the ground pin, sense pin is, t he logic power supply pin vdd, the spi pins, input pins, external driver pins and the limp home input pin has to be limited as well (please re fer to the maximum ratings listed on page 10 ). note: no protection mechanism like temper ature protection or current protection is active during reverse polarity. 7.7 over voltage protection in the case of supply voltages between v s(sc)max and v s(cl) the output transistors ar e still operational and follow the input or the outl register. parameters are not warranted and lif etime is reduced compared to normal mode. in addition to the output clamp for inductive loads as described in section 6.3 , there is a clamp mechanism available for over voltage protec tion of the internal circuits. 7.8 loss of ground in case of complete loss of the device ground co nnections, but connected load ground, the spoc - BTS5482SF securely changes to or stays in off-state. 7.9 loss of v s in case of loss of v s connection in on-state, all inductances of the loads have to be demagnetized through the ground connection or through an additional path fr om vs to gnd. for example, a suppressor diode is recommended between vs and gnd. fault inrush i l t t err t vs_undervoltage.emf i l(htrip) in / outx i l( l tr i p ) v s t v s(nor) v s( mo n) startup * err-flag will be reset by standard diagnosis readout during restart ** current trip level reduced due to v s undervoltage n retr y latch off due to n retry (lv ) 0 1 2 3 4 31 32
spoc - BTS5482SF protection functions data sheet 35 rev. 1.0, 2013-06-05 7.10 electrical characteristics electrical characteri stics protection functions unless otherwise specified: v s = 8 v to 17 v, v dd = 3.0 v to 5.5 v, t j = -40 c to +150 c typical values: v s = 13.5 v, v dd = 4.3 v, t j = 25 c pos. parameter symbol limit values unit test conditions min. typ. max. over current protection 7.10.1 load current trip level i l(htrip) a v ds < 7 v channel 0, 1 71 ? 67 ? 90 ? 120 ? 100 t j = -40 c 1) t j = 25 c t j = 150 c channel 2, 3 29 ? 23 ? 30 ? 44 ? 39 hwcr.ledn = 0 t j = -40 c 1) t j = 25 c t j = 150 c 7 ? 5.5 ? 8.5 ? 12 ? 11 hwcr.ledn = 1 t j = -40 c 1) t j = 25 c t j = 150 c 7.10.2 operative state activation time t delay(ltrip) 71014ms 1) 7.10.3 inrush state re-activation time t delay(htrip) ? 160 250 ms 1) 7.10.4 load current trip level after t delay(ltrip) i l(ltrip) a channel 0, 1 40 35 ? ? 78 70 t j = -40 c t j = 150 c channel 2, 3 17 15.5 ? ? 35 30 hwcr.ledn = 0 t j = -40 c t j = 150 c 3.8 3.8 ? ? 9 8 hwcr.ledn = 1 t j = -40 c t j = 150 c 7.10.5 load current trip level at high v ds i l(vtrip) a 1) channel 0, 1 40 35 ? ? 78 70 t j = -40 c t j = 150 c channel 2, 3 17 15.5 ? ? 35 30 hwcr.ledn = 0 t j = -40 c t j = 150 c 3.8 3.8 ? ? 9 8 hwcr.ledn = 1 t j = -40 c t j = 150 c 7.10.6 over current tripping at high v ds activation level v ds(vtrip) 15 20 ? v 1) 7.10.7 v s monitoring threshold v s(mon) ?5.7?v 1)
data sheet 36 rev. 1.0, 2013-06-05 spoc - BTS5482SF protection functions over temperature protection 7.10.8 number of automatic retries at over current or dynamic temperature sensor shut down at low v ds n retry(lv) ??32 1) v ds = 9 v 7.10.9 number of automatic retries at over current or dynamic temperature sensor shut down at medium v ds n retry(mv) ??8 1) v ds = 13 v 7.10.10 thermal shut down temperature t j(sc) 150 180 210 c 1) 7.10.11 thermal hysteresis of thermal shutdown ? t j ?15?k 1) 7.10.12 dynamic temperature sensor restart ? t j(res) ?35?k 1) reverse battery 7.10.13 o n - s t a t e r e s i s t a n c e r ds(rev) m 1) v s = -13.5 v channel 0, 1 ? ? 4 6 ? ? i l = -7.5 a t j = 25 c t j = 150 c channel 2, 3 ? ? 15 21 ? ? i l = -2.6 a t j = 25 c t j = 150 c over voltage 7.10.14 over voltage protection v s(cl) v vs to gnd 40 60 71 i gnd = 5 ma channel 0, 1 32 40 ? ? 54 55 t j = 25 c i l = 20 ma 1) t j = 150 c i l = 6 a channel 2, 3 32 40 ? ? 54 55 t j = 25 c i l = 20 ma 1) t j = 150 c i l = 2 a 1) not subject to production test, specified by design. electrical characterist ics protection functions (cont?d) unless otherwise specified: v s = 8 v to 17 v, v dd = 3.0 v to 5.5 v, t j = -40 c to +150 c typical values: v s = 13.5 v, v dd = 4.3 v, t j = 25 c pos. parameter symbol limit values unit test conditions min. typ. max.
spoc - BTS5482SF diagnosis data sheet 37 rev. 1.0, 2013-06-05 8 diagnosis for diagnosis purpose, the spoc - BTS5482SF provides a cu rrent sense signal at pin is and the diagnosis word via spi. there is a current sense multiplexer implemented that is controlled via spi. the sense signal can also be disabled by spi command. a switch bypass monitor allows to detect a short circuit between the output pin and the battery voltage. in off-state a current source is able to be switched on for a selected channel with the dcr.csol bit. this allows open load / short circuit detection to v s in off-state. the current value can be configured to a low or a high value by programming the bit icr.csl . please refer to parameter i l(ol) ( 8.5.16 ). note: all parameters and functions stated below are valid for the internal channels. the behavior of the current sense of the two external channel is restricted to the behavior of the external drivers. please refer to figure 20 for details on diagnosis function: figure 20 block diagram: diagnosis channel 0 load cur rent sense diagnosis_std.emf r is i is 0 curr ent sense m ultiplexer is t gate contr ol latch tem per atur e sensor err0 or latch dcr.mux v s v ds(sb) sbm dcr. out3 out2 out1 out0 vs csol over cur rent protection i l(ol)
data sheet 38 rev. 1.0, 2013-06-05 spoc - BTS5482SF diagnosis for diagnosis feedback at different oper ation modes, please see following table. 8.1 diagnosis word at spi the standard diagnosis at the spi in terface provides information about each channel. the error flags, an or combination of the over temperature flags and the over lo ad monitoring signals are provided in the spi standard diagnosis bits errn . the over load monitoring signals are latched in the erro r flags and cleared each time the standard diagnosis is transmitted via spi. in detail, they are cleared between the second and third raising edge of the sclk signal. the over temperature flags, which cause an overheated channel to latch off, are latched directly at the gate control block. the over current flags, which cause a channel driv ing a too high current to switch off, are latched like the over temperature flags. those latches are cleared by spi command hwcr.cl . note: the over temperature and over current informatio n is latched twice. when transmitting a clear latch command ( hwcr.cl ), the error flag is cleared during comma nd transmission of the next spi frame and ready for latching after the third raising edge of the sc lk signal. as a result, the first standard diagnosis information after a clear la tch command will indicate a failure mode at the previously affected channels although the thermal latches have been cleared already. in case of continuous over load, the error flags are set again immediately because of the over load monitoring signal. table 7 operation modes 1) 1) l = low level, h = high level, z = high impedance, potential d epends on leakage currents and external circuit x = undefined operation mode input level outl.outn output level v out current sense i is error flag errn 2) 2) the error flags are latched until they are tr ansmitted in the standard diagnosis word via spi sbm dcr.sbm normal operation (off) l / 0 (off-state) gnd z 0 1 short circuit to gnd gnd z 0 1 thermal shut down z z 0 x short circuit to v s v s z 0 0 open load z z 0 0 3) 3) if the current sense multiplexer is set to channel 0 to 3 and dcr.csol bit set inverse current > v s z 0 0 4) 4) if the current sense multiplexer is set to channel 0 to 3 normal operation (on) h / 1 (on-state) ~ v s i l / k ilis 00 short circuit to gnd ~ gnd z 1 1 dynamic temperature sensor shut down z z 1 x over current shut down z z 1 5) 5) the over current latch off flag is set la tched and can be cleared by spi command hwcr.cl x thermal shut down z z 1 6) 6) the over temperature flag is set latc hed and can be cleared by spi command hwcr.cl x short circuit to v s v s < i l / k ilis 00 open load v s z00 inverse current > v s z00
spoc - BTS5482SF diagnosis data sheet 39 rev. 1.0, 2013-06-05 8.2 load current sense diagnosis there is a current sense signal available at pin is which provides a current proportional to the load current of one selected channel. the selection is done by a multiplexer which is configured via spi. current sense signal the current sense signal (ratio k ilis = i l / i s ) is provided during on-state as long as no failure mode occurs. the ratio k ilis can be adjusted to the load type (led or bulb) via spi register hwcr for channel 2 and 3. the accuracy of the ratio k ilis depends on the load current. usually a resistor r is is connected to the current sense pin. it is recommended to use resistors 1.5 k ? < r is <5k ? . a typical value is 2.7 k ? . figure 21 current sense ratio k ilis channel 0, 1 1) figure 22 current sense ratio k ilis channel 2, 3 (bulb) 1) 1) the curves show the behavior based on characterization dat a. the marked points are guaranteed in this data sheet in section 8.5 (position 8.5.1 and 8.5.2 ). 0 5000 10000 15000 20000 25000 30000 012345678 k ilis value load current i l [a] kilis tj = -40 c kilis typ tj = 25 c kilis tj = 25 c, 150 c 0 2000 4000 6000 8000 10000 12000 14000 00.511.522.533.544.5 k ilis value load current i l [a] kilis bulb tj = 25 c, 150 c kilis bulb typ tj = 25 c kilis bulb tj = -40 c
data sheet 40 rev. 1.0, 2013-06-05 spoc - BTS5482SF diagnosis figure 23 current sense ratio k ilis channel 2, 3 (led) 1) in case of off-state, over current, dynamic temperature sensor latch as well as over temperature, the current sense signal of the affected channel is switched off. to distinguish between a latche d and non latched flag, the spi diagnosis word can be used. the over current shut down flag ( n < n retry ) is cleared every time the diagnosis is transmitted, whereas the over temperat ure latch, dynamic temperature protection latch and over current latch is cleared by a dedicated spi command ( hwcr.cl ). details about timings between the current sense signal i is and the output voltage v out and the load current i l can be found in figure 24 . figure 24 timing of current sense signal current sense multiplexer there is a current sense multiplexer implemented in the spoc - BTS5482SF that routes the sense current of the selected channel to the diagnosis pin is. the channel is selected via spi register dcr.mux . the sense current also can be disabled by spi register dcr.mux . for details on timing of the current sense multiplexer, please refer to figure 25 . the current sense diagnosis enable signal for the exter nal smart power drivers also can be selected via the spi register dcr.mux. for being compliant to profet+ diagnostic functi ons, it is possible to configure pin edd0 as den and edd1 as dsel. therefore, the bit outh.pro+ needs to be set. 0 200 400 600 800 1000 1200 1400 0 0.2 0.4 0.6 0.8 1 k ilis value load current i l [a] kilis led tj = 25 c, 150 c kilis led typ tj = 25 c kilis led tj = -40 c sensetiming.emf v out i is t t t i l t on t on t sis(on) t sis(lc) off t off t dis(off ) off outx
spoc - BTS5482SF diagnosis data sheet 41 rev. 1.0, 2013-06-05 figure 25 timing of current sense multiplexer current sense of fset trimming to increase the current sense accuracy of spoc - BTS5482SF, a circuitry to measure and trim the sense offset current is implemented. this so called calibra tion mode is activated by the spi command icr.cal = 1 b . in calibration mode, a current proportional to the positive offs et of the operational amplifier is provided on the is pin. to increase the accura cy of the calibration this cu rrent is amplified when calibra tion mode is entered (see 8.5.4 ). the offset of the operational amplifier can be tri mmed by 15 steps which are selected by the bits kilis.ostn . (see. chapter 9.6 for detailed information). to exit the calibration mode icr.cal is set to 0 b . during calibration the state of the current sense multiplexer should no t be changed, otherwise the measured current could be affected. if dcr.mux = 111 the device exits calibration mode and st and-by mode is entered. in general the calibration mode does not have any effect on other spi regi sters or functions of the device. in case of calibration during operation switching transients on the supply line must be considered. 8.3 switch bypass diagnosis to detect short circuit to v s , there is a switch bypass monitor implemented for all internal channels. in case of short circuit between the output pin out and v s in on-state, the current will flow through the power transistor as well as through the s hort circuit (bypass) with undefin ed ratio. as a result, the current sense signal will show lower values than expected by the load current. in o ff-state, the output vo ltage will stay close to v s potential which means a small v ds . the time for the output voltage to reach a stea dy state condition depends on the time constant of the respective output pin which is affected by the resistance and capacitance introduced by external components and the board layout. the switch bypass monitor compares the voltage v ds across the power transistor of that channel, which is selected by the current sense multiplexer ( dcr.mux ) with threshold v ds(sb) . the result of the comparison can be read in spi register dcr.sbm or in the standard diagnosis. 8.4 open load in off-state for performing a dedicated open load in off-state dete ction a current source can be switched in parallel to the dmos accord ing to the figure 20 . the current source current can be programmed in two steps by the bit icr.csl . the following procedure is recommended to use: ? select the dedicated channel with the multiplexer ? enable the open load current with the dcr.csol bit ? read the dcr.sbm or the standard diagnosis ? disable the open load current with the dcr.csol bit note: to distinguish between a short circuit to v s and an open load in off-state, a pull-down resistor at the output would be needed to compensate the output leakage of the channel. muxtiming.emf cs i is t t 010 dcr.mux 000 110 110 t s is( en ) t sis(mux) t dis (mux)
data sheet 42 rev. 1.0, 2013-06-05 spoc - BTS5482SF diagnosis 8.5 electrical characteristics electrical characteristics diagnosis unless otherwise specified: v s = 8 v to 17 v, v dd = 3.0 v to 5.5 v, t j = -40 c to +150 c typical values: v s = 13.5 v, v dd = 4.3 v, t j = 25 c pos. parameter symbol limit values unit test conditions min. typ. max. load current sense 8.5.1 current sense ratio k ilis t j = -40 c channel 0, 1: 0.456 a 0.600 a 1.3 a 2.6 a 4.0 a 7.5 a 1800 2200 4100 5030 5300 5600 6900 6700 6400 6400 6450 6450 29000 20000 10500 8200 7800 7300 ? ? ? ? ? ? channel 2, 3 (bulb): hwcr.ledn = 0 0.115 a 0.300 a 0.600 a 1.3 a 2.6 a 4.0 a 585 1000 1300 1500 1600 1600 2000 1830 1830 1830 1840 1840 13000 3630 2600 2100 2080 2080 ? ? ? ? ? ? channel 2, 3 (led): hwcr.ledn = 1 0.050 a 0.150 a 0.300 a 0.600 a 1.0 a 170 300 350 400 400 400 440 450 460 500 1300 675 580 555 555 ? ? ? ? ? 8.5.2 current sense ratio k ilis t j = 25 c to 150 c channel 0, 1: 0.456 a 0.600 a 1.3 a 2.6 a 4.0 a 7.5 a 2700 3200 4500 5030 5300 5600 6000 6100 6350 6400 6450 6450 15000 10500 9100 8200 7800 7300 ? ? ? ? ? ? channel 2, 3 (bulb): hwcr.ledn = 0 0,115 0.300 a 0.600 a 1.3 a 2.6 a 4.0 a 600 1000 1300 1500 1600 1600 1750 1790 1810 1830 1840 1840 7000 2600 2300 2100 2080 2080 ? ? ? ? ? ?
spoc - BTS5482SF diagnosis data sheet 43 rev. 1.0, 2013-06-05 channel 2, 3 (led): hwcr.ledn = 1 0.050 a 0.150 a 0.300 a 0.600 a 1.0 a 170 300 350 400 400 400 440 450 460 500 800 640 580 555 555 ? ? ? ? ? 8.5.3 current sense drift of unaffected channel during inverse current of other channels channel 0, 1 channel 2, 3 (bulb) channel 2, 3 (led) ? k ilis(ic) -20 % -20 % -20 % -20 % -20 % -20 % ? ? ? ? ? ? 20 % 20 % 20 % 20 % 20 % 20 % 1) dcr.mux 111 i l0, 1 = 7.5 a i l1, 0 (ic) = 7.5 a i l2, 3 (ic) = 2.6 a hwcr.ledn = 0 i l2, 3 = 2.6 a i l0, 1 (ic) = 7.5 a i l3, 2 (ic) = 2.6 a hwcr.ledn = 1 i l2, 3 = 0.6 a i l0, 1 (ic) = 7.5 a i l3, 2 (ic) = 2.6 a 8.5.4 calibration step i is(cal) ? ? 5 75 ? ? a 1) t j = 25 c icr.cal = 0 icr.cal = 1 8.5.5 current sense voltage limitation v is(lim) 89.511v 1)2) i is = 3ma 8.5.6 maximum steady state current sense output current i is(max) 5.5 ? 20 ma 1) v is = 0 v 8.5.7 current sense leakage / offset current channel 0, 1 channel 2, 3 i is(en) ? ? ? ? 70 70 a i l = 0 a dcr.mux 111 icr.cal = 0 kilis.ostn = 1000 8.5.8 current sense leakage, while diagnosis disabled i is(dis) ??1a dcr.mux = 110 icr.cal = 0 electrical characteristics diagnosis (cont?d) unless otherwise specified: v s = 8 v to 17 v, v dd = 3.0 v to 5.5 v, t j = -40 c to +150 c typical values: v s = 13.5 v, v dd = 4.3 v, t j = 25 c pos. parameter symbol limit values unit test conditions min. typ. max.
data sheet 44 rev. 1.0, 2013-06-05 spoc - BTS5482SF diagnosis 8.5.9 current sense settling time after channel activation channel 0, 1 t sis(on) ??150 s v s = 13.5 v r is = 2.7 k ? r l = 2.2 ? channel 2, 3 ? ? ? ? 150 100 hwcr.ledn = 0 r l = 6.8 ? hwcr.ledn = 1 r l = 33 ? 8.5.10 current sense de settling time after channel deactivation t dis(off) ? ? ? ? 25 25 s 1) v s = 13.5 v r is = 2.7 k ? hwcr.ledn = 0 hwcr.ledn = 1 8.5.11 current sense settling time after change of load current channel 0, 1 t sis(lc) ??30 s 1) v s = 13.5 v r is = 2.7 k ? i l = 7.5 a to 4.0 a channel 2, 3 ? ? ? ? 30 30 hwcr.ledn = 0 i l = 2.6 a to 1.3 a hwcr.ledn = 1 i l = 0.6 a to 0.3 a 8.5.12 current sense settling time after current sense activation t sis(en) ??25s r is = 2.7 k ? dcr.mux : 110 -> 000 8.5.13 current sense settling time after multiplexer channel change t sis(mux) ??30s r is = 2.7 k ? r l0 = 2.2 ? r l2 = 33 ? dcr.mux : 010 -> 000 8.5.14 current sense deactivation time t dis(mux) ??25s 1) r is = 2.7 k ? dcr.mux : 000 -> 110 switch bypass monitor 8.5.15 switch bypass monitor threshold v ds(sb) 1.5 ? 4 v ? open load in off current source 8.5.16 current source in off-state i l(ol) 100 3.0 ? ? 450 7.5 a ma icr.csl = 0 icr.csl = 1 1) not subject to production test, specified by design. 2) voltage clamp at current sense pin has to be considered as a protection feature. electrical characteristics diagnosis (cont?d) unless otherwise specified: v s = 8 v to 17 v, v dd = 3.0 v to 5.5 v, t j = -40 c to +150 c typical values: v s = 13.5 v, v dd = 4.3 v, t j = 25 c pos. parameter symbol limit values unit test conditions min. typ. max.
spoc - BTS5482SF serial peripheral interface (spi) data sheet 45 rev. 1.0, 2013-06-05 9 serial peripheral interface (spi) the serial peripheral interface (spi) is a full duplex sync hronous serial slave interface, which uses four lines: so, si, sclk and cs . data is transferred by the lines si and so at the rate given by sclk. the falling edge of cs indicates the beginning of an access. da ta is sampled in on line si at the falling edge of sclk and shifted out on line so at the rising edge of sclk. each access must be terminated by a rising edge of cs . a modulo 8 counter ensures that data is taken only, when a multiple of 8 bit has been transferr ed. the interface provides daisy chain capability. figure 26 serial peripheral interface 9.1 spi signal description cs - chip select: the system micro controller selects the spoc - BTS5482SF by means of the cs pin. whenever the pin is in low state, data transfer can take place. when cs is in high state, any signals at the sclk and si pins are ignored and so is forced into a high impedance state. cs high to low transition: ? the requested information is transferred into the shift register. ? so changes from high impedance state to high or lo w state depending on the logi c or combination between the transmission error flag ( ter ) and the signal level at pin si. as a re sult, even in daisy chain configuration, a high signal indicates a faulty transmission. this inform ation stays available to the first rising edge of sclk. figure 27 combinatorial logic for ter flag lsb 6 5 4 3 2 1 lsb 6 5 4 3 2 1 cs msb msb so si cs sclk time spi.emf ter.emf si spi or ter 0 1 so cs sclk s so s si
data sheet 46 rev. 1.0, 2013-06-05 spoc - BTS5482SF serial peripheral interface (spi) cs low to high transition: ? command decoding is only done, when after the falling edge of cs exactly a multiple (1, 2, 3, ?) of eight sclk signals have been detected. in case of faul ty transmission, the transmission error flag ( ter ) is set and the command is ignored. ? data from shift register is transferred into the addressed register. sclk - serial clock: this input pin clocks the in ternal shift register. the serial input (si) transfers da ta into the shift register on the falling edge of sclk while the serial output (s o) shifts diagnostic information out on the rising edge of the serial clock. it is essential that the sclk pin is in low state whenever chip select cs makes any transition. si - serial input: serial input data bits are shift-in at this pin, the most significant bit first. si information is read on the falling edge of sclk. the input data consists of two parts, co ntrol bits followed by dat a bits. please refer to section 9.5 for further information. so serial output: data is shifted out serially at this pin, the most significant bit first. so is in high impedance state until the cs pin goes to low state. new data will appe ar at the so pin following the risi ng edge of sclk. please refer to section 9.5 for further information. 9.2 daisy chain capability the spi of spoc - BTS5482SF provides daisy chain capability. in this configuration se veral devices are activated by the same cs signal mcs . the si line of one device is connecte d with the so line of another device (see figure 28 ), in order to build a chain. the ends of the chain are connected with the output and input of the master device, mo and mi respectively. the ma ster device provides the master cl ock mclk which is connected to the sclk line of each device in the chain. figure 28 daisy chain configuration si device 1 spi sclk so cs si device 2 spi sclk so cs si device 3 spi sclk so cs mo mi mcs mclk spi _daisychain . emf
spoc - BTS5482SF serial peripheral interface (spi) data sheet 47 rev. 1.0, 2013-06-05 in the spi block of each device, there is one shift register where one bit from si line is shifted in each sclk. the bit shifted out occurs at the so pin. after eight sclk cyc les, the data transfer for one device has been finished. in single chip configuration, the cs line must turn high to make the devic e accept the transferred data. in daisy chain configuration, the data shifted out at device 1 ha s been shifted in to device 2. when using three devices in daisy chain, three times eight bits have to be shifted through the devices. after that, the mcs line must turn high (see figure 29 ). figure 29 data transfer in daisy chain configuration 9.3 timing diagrams figure 30 timing diagram spi access mi mo mcs mclk si device 1 si device 2 si device 3 so device 1 so device 2 so device 3 time spi_daisychain2.emf cs sclk si t cs(lead) t cs( td ) t cs( l a g ) t scl k( h) t scl k( l ) t scl k( p) t si( su ) t si( h ) so t so( v) t so( e n ) t so( d is) 0. 7 v dd 0. 2 v dd 0. 7 v dd 0. 2 v dd 0. 7 v dd 0. 2 v dd 0. 7 v dd 0. 2 v dd spi t iming. emf
data sheet 48 rev. 1.0, 2013-06-05 spoc - BTS5482SF serial peripheral interface (spi) 9.4 electrical characteristics electrical characteristics seri al peripheral interface (spi) unless otherwise specified: v s = 8 v to 17 v, v dd = 3.0 v to 5.5 v, t j = -40 c to +150 c typical values: v s = 13.5 v, v dd = 4.3 v, t j = 25 c pos. parameter symbol limit values unit test conditions min. typ. max. input characteristics (cs , sclk, si) 9.4.1 l level of pin cs sclk si v cs(l) v sclk(l) v si(l) 0 ? 0.2* v dd v v dd = 4.3 v 9.4.2 h level of pin cs sclk si v cs(h) v sclk(h) v si(h) 0.4* v dd ? v dd v v dd = 4.3 v 9.4.3 pull-up resistor at cs pin r cs 50 120 180 k ? 1) 9.4.4 pull-down resistor at pin sclk si r sclk r si 50 120 180 k ? 1) output characteristics (so) 9.4.5 l level output voltage v so(l) 0?0.4v i so = -0.5 ma 9.4.6 h level output voltage v so(h) v dd - 0.4 v ? v dd v i so = 0.5 ma v dd = 4.3 v 9.4.7 output tristate leakage current i so(off) -10 ? 10 a v cs = v dd timings 9.4.8 serial clock frequency f sclk 0 0 ? ? 5 3 mhz 1) v dd = 4.3 v 2) v dd = 3.0 v 9.4.9 serial clock period t sclk(p) 200 333 ? ? ? ? ns 1) v dd = 4.3 v 2) v dd = 3.0 v 9.4.10 serial clock high time t sclk(h) 100 166 ? ? ? ? ns 1) v dd = 4.3 v 2) v dd = 3.0 v 9.4.11 serial clock low time t sclk(l) 100 166 ? ? ? ? ns 1) v dd = 4.3 v 2) v dd = 3.0 v 9.4.12 enable lead time (falling cs to rising sclk) t cs(lead) 200 333 ? ? ? ? ns 1) v dd = 4.3 v 2) v dd = 3.0 v 9.4.13 enable lag time (falling sclk to rising cs ) t cs(lag) 200 333 ? ? ? ? ns 1) v dd = 4.3 v 2) v dd = 3.0 v 9.4.14 transfer delay time (rising cs to falling cs ) t cs(td) 200 333 ? ? ? ? ns 1) v dd = 4.3 v 2) v dd = 3.0 v 9.4.15 data setup time (required time si to falling sclk) t si(su) 20 33 ? ? ? ? ns 1) v dd = 4.3 v 2) v dd = 3.0 v 9.4.16 data hold time (falling sclk to si) t si(h) 20 33 ? ? ? ? ns 1) v dd = 4.3 v 2) v dd = 3.0 v
spoc - BTS5482SF serial peripheral interface (spi) data sheet 49 rev. 1.0, 2013-06-05 9.4.17 output enable time (falling cs to so valid) t so(en) ? ? ? ? 200 333 ns 2) c l = 20 pf v dd = 4.3 v v dd = 3.0 v 9.4.18 output disable time (rising cs to so tri-state) t so(dis) ? ? ? ? 200 333 ns 2) c l = 20 pf v dd = 4.3 v v dd = 3.0 v 9.4.19 output data valid time with capacitive load t so(v) ? ? ? ? 100 166 ns 2) c l = 20 pf v dd = 4.3 v v dd = 3.0 v 1) not subject to production test, specified by design. spi functional test is performed at f sclk = 5 mhz. 2) not subject to production test, specified by design. electrical characteristics seri al peripheral interface (spi) (cont?d) unless otherwise specified: v s = 8 v to 17 v, v dd = 3.0 v to 5.5 v, t j = -40 c to +150 c typical values: v s = 13.5 v, v dd = 4.3 v, t j = 25 c pos. parameter symbol limit values unit test conditions min. typ. max.
data sheet 50 rev. 1.0, 2013-06-05 spoc - BTS5482SF serial peripheral interface (spi) 9.5 spi protocol 8 bit note: reading a register needs two spi frames. in the first frame the rd command is sent. in the second frame the output at spi signal so will cont ain the requested information. a ne w command can be executed in the second frame. the standard diagnosis can be access ed either by sending the standard diagnosis read command or it is transmitted after each write command. cs 1) 1) the so pin shows this information between cs hi -> lo and first sclk lo -> hi transition. 76543210 write outl, outh and kilis register si 1 0 addr data read outl, outh and kilis register si 0 0 addr x x x 0 write configuration and control registers si 1 1 addr data read configuration and control registers si 0 1 addr x x x 0 read standard diagnosis si 0xxxxxx1 standard diagnosis so ter 0 lhi sbm x err3 err2 err1 err0 second frame of read command so ter 1 0 out5 out4 out3 out2 out1 out0 so ter 1 1 addr data field bits type description w/r 7 w 0 read 1write rb 6 r register bank 0 read / write to outl, outh and kilis register 1 read / write to the other register ter cs r transmission error 0 previous transmission was successful (modulo 8 clocks received) 1 previous transmission failed or first transmission after reset addr 6:5 rw address pointer to register for read and write command data 4:0 rw data data written to or read from register selected by address addr errn n = 3 to 0 nr diagnosis of channel n 1) 0 no failure 1 over temperature, over current, over load or short circuit for channel 0 to 3 sbm 5 r switch bypass monitor 2) 0 v ds < v ds(sb) 1 v ds > v ds(sb)
spoc - BTS5482SF serial peripheral interface (spi) data sheet 51 rev. 1.0, 2013-06-05 9.6 register overview note: a readout of an u nused register will return the standard diagnosis. outn n = 5 to 0 nr output status for channel n 0 channel is switched off 1 channel is switched on lhi 6 r limp home enable 3) 0 h-input signal at lhi pin 1 l-input signal at lhi pin 1) no err-flags available for external drivers 2) invalid in stand-by mode 3) not latching information, read of lhi-status during falling cs rb address name description 0 0 0 outl output configuration register low 0 0 1 outh output configuration register high 0 1 0 kilis current sense offset calibration register 0 1 1 sccr short circuit configuration register 1 0 1 icr input and current source configuration register 1 1 0 hwcr hardware configuration register 1 1 1 dcr diagnosis control register bit 76543210 name w/r rb addr data default 1) 1) the default values are set after reset. outl w/r 0 0 0 out3 out2 out1 out0 80 h outh w/r 0 0 1 pro+ res. out5 out4 90 h kilis w/r 0 1 0 ost3 ost2 ost1 ost0 a8 h sccr w/r 0 1 1 itc3 itc2 itc1 itc0 b0 h icr w/r 1 0 1 col incg csl cal d0 h hwcr r 1 1 0 led3 led2 stb cl e2 h w 1 1 0 led3 led2 rst cl - dcr r 1 1 1 sbm mux f7 h w1 1 1csol mux - field bits type description
data sheet 52 rev. 1.0, 2013-06-05 spoc - BTS5482SF serial peripheral interface (spi) field bits type description outl n = 3 to 0 nrw output control register for channel 0 to 3 0 off 1on outh n = 3 to 0 nrw output control register for channel 4, 5 and pro+ bit 0 off 1on pro+ 0 rw configuration of edd0 and edd1 to be compliant to profet+ concept 0 normal mode 1 edd0=den, edd1=dsel ostn n = 3 to 0 nrw is offset trimming 0000 i is(en) - 8 x i is(cal) 0001 i is(en) - 7 x i is(cal) 0010 i is(en) - 6 x i is(cal) 0011 i is(en) - 5 x i is(cal) 0100 i is(en) - 4 x i is(cal) 0101 i is(en) - 3 x i is(cal) 0110 i is(en) - 2 x i is(cal) 0111 i is(en) - 1 x i is(cal) 1000 i is(en) without offset calibration 1001 i is(en) + 1 x i is(cal) 1010 i is(en) + 2 x i is(cal) 1011 i is(en) + 3 x i is(cal) 1100 i is(en) + 4x i is(cal) 1101 i is(en) + 5 x i is(cal) 1110 i is(en) + 6 x i is(cal) 1111 i is(en) + 7 x i is(cal)) itcn n = 3 to 0 nrw inrush timer control 0 timer t delay(htrip) will run only in off state of respective channel 1timer t delay(htrip) will run in on and off stat e of respective channel cal 0 rw is offset calibration 0 calibration mode is deactivated 1 calibration mode is activated csl 1 rw level for current source for open load detection 0 low level 1 high level incg 2 rw input drive configuration 0 direct drive mode 1 assigned drive mode col 3 rw input combinatorial logic configuration 0 input signal or-combined with according outl register bit 1 input signal and-combined with according outl register bit stb 1 r standby mode 0 device is awake 1 device is in standby mode
spoc - BTS5482SF serial peripheral interface (spi) data sheet 53 rev. 1.0, 2013-06-05 ledn n = 3 to 2 nrw set led mode for channel n 0 channel n is in bulb mode 1 channel n is in led mode cl 0 rw clear latch 0 thermal and over current latches are untouched 1 command: clear all thermal and over current latches rst 1 w reset command 0 normal operation 1 execute reset command mux 2:0 rw set current sense multiplexer configuration in off-state 000 is pin is high impedance 001 is pin is high impedance 010 is pin is high impedance 011 is pin is high impedance 100 outh.pro+ = 0: diagnosis enable of external driver 0 activated (edd0 = 1) 101 outh.pro+ = 0: diagnosis enable of external driver 1 activated (edd1 = 1) 100 outh.pro+ = 1: edd0 = 1, edd1 = 0 101 outh.pro+ = 1: edd0 = 1, edd1 = 1 110 is pin is high impedance 111 stand-by mode (is pin is high impedance) set multiplexer configuration in on-state 000 current sense of channel 0 is routed to is pin 001 current sense of channel 1 is routed to is pin 010 current sense of channel 2 is routed to is pin 011 current sense of channel 3 is routed to is pin 100 outh.pro+ = 0: diagnosis enable of external driver 0 activated (edd0 = 1) 101 outh.pro+ = 0: diagnosis enable of external driver 1 activated (edd1 = 1) 100 outh.pro+ = 1: edd0 = 1, edd1 = 0 101 outh.pro+ = 1: edd0 = 1, edd1 = 1 110 is pin is high impedance 111 stand-by mode (is pin is high impedance)) sbm 3 r switch bypass monitor 1) 0 v ds < v ds(sb) 1 v ds > v ds(sb) csol 3 w current source switch fo r open load detection 0 off 1on 1) invalid in stand-by mode field bits type description
data sheet 54 rev. 1.0, 2013-06-05 spoc - BTS5482SF application description 10 application description figure 31 application circuit example 1 spi vs out3 out2 out1 out0 65 w 65 w 27 w 10 w external driver control is so sclk si cs gnd lhi edd1 edd0 edo0 edo1 vdd gnd circuit _std _ext.emf vdd 100nf c e .g. xc2267 vss vcc v bat ad 5v 500 ? 2.7k ? 1k ? 1n f spi 3. 9 k ? 3. 9 k ? 3. 9 k ? 3. 9 k ? 8k ? 8k ? gpio gpio in2 in3 in1 wd-out 10 ? 2 1 for filtering and protection purposes 2 for increased iso-pulse robustness 3 for improved electromagnetic compatibility (emc) 100nf 3 profet ch1 in1 in2 out0 vs profet ch2 dsel gnd out1 den is wd-out 8k ? 10k ? 10nf 3 100nf 3
spoc - BTS5482SF package outlines spoc - BTS5482SF data sheet 55 rev. 1.0, 2013-06-05 11 package outlines spoc - BTS5482SF figure 32 pg-dso-36-43 (plastic dual small outline package) green product (rohs compliant) to meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. green products are rohs-compliant (i.e pb-free finish on leads and suitable for pb-free soldering according to ipc/jedec j-std-020). gps01089 2) does not include dambar protrusion of 0.05 max. per side 1) does not include plastic or metal protrusion of 0.15 max. per side 1 18 36 19 0.65 0.33 0.2 2.45 2.65 max. 0.1 -0.2 -0.1 0.23 +0.09 0.35 x 45? -0.2 1) 7.6 10.3 0.7 ?.2 8? max. ?.3 index marking 1) 12.8 -0.2 18 1 19 36 index marking ejector mark bottom view 0.17 m c a-b d 36x ?.08 2) c d a b dimensions in mm you can find all of our packages, sorts of pa cking and others in our infineon internet page ?products?: http://www.infineon.com/products .
spoc - BTS5482SF revision history data sheet 56 rev. 1.0, 2013-06-05 12 revision history trademarks of infineon technologies ag aurix?, c166?, canpak?, ci pos?, cipurse?, econopac k?, coolmos?, coolset?, corecontrol?, crossav e?, dave?, di-pol?, easypim?, econobridge?, econodual?, econopim?, econopack?, eicedriver?, eupec?, fcos?, hitfet?, hybridpack?, i2rf?, isoface?, isopack?, mipaq?, modstack?, my-d?, novalithic?, optimos?, origa?, powercode?; primarion?, pr imepack?, primestack?, pr o-sil?, profet?, rasic?, reversave?, satric?, si eget?, sindrion?, sipmos?, smartl ewis?, solid flash?, tempfet?, thinq!?, trenchstop?, tricore?. other trademarks advance design system? (ads) of agilent te chnologies, amba?, arm?, multi-ice?, keil?, primecell?, realview?, thumb?, vision? of arm limited, uk. autosar? is licensed by autosar development partnership. bluetooth? of bluetooth sig inc. cat-iq? of dect forum. colossus?, firstgps? of trimble navigation ltd. emv? of emvc o, llc (visa holdings in c.). epcos? of epcos ag. flexgo? of microsoft corp oration. flexray? is licensed by flexray consortium. hyperterminal? of hilgraeve incorporated. iec? of commission electrot echnique internationale. irda? of infrared data association corporation. iso? of international organization for standardization. matlab? of mathworks, inc. maxim? of maxim integrated products, inc. microtec?, nucleus? of mentor graphics corporation. mipi? of mipi allianc e, inc. mips? of mips technologies, inc., u sa. murata? of murata manufacturing co., microwave office? (mwo) of applied wave research inc., omnivision? of omnivision technologies, inc. openwave? openwave systems inc. red hat? red hat, inc. rfmd? rf micro devices, inc. sirius? of si rius satellite radio inc. solaris? of sun microsystems, inc. spansion? of spansion llc ltd. symbian? of symbian software limited. taiyo yuden? of taiyo yuden co. teaklite? of ceva, inc. tektro nix? of tektronix inc. toko? of toko kabushiki kaisha ta. unix? of x/open company limited. verilo g?, palladium? of cadence design systems, inc. vlynq? of texas instruments incorpor ated. vxworks?, wind river? of wind ri ver systems, inc. zetex? of diodes zetex limited. last trademarks update 2011-11-11 revision date changes 1.0 2013-06-05 data sheet
edition 2013-06-05 published by infineon technologies ag 81726 munich, germany ? 2013 infineon technologies ag all rights reserved. legal disclaimer the information given in this docu ment shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infine on technologies hereby disclaims any and all warranties and liabilities of any kind, including witho ut limitation, warranties of non-infrin gement of intellectua l property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies compon ents may be used in life-su pport devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safe ty or effectiveness of that de vice or system. life support devices or systems are intended to be implanted in the hu man body or to support an d/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

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